Reducing Parasitics In Finfet Layouts.

With VLSI industry following Moore’s law for many decades, which says, “the number of transistors on a chip becomes double approximately every two years”,the density of devices on chip has gone high and as all layouts are made by following minimum DRC rules,it gives birth to a new significant effect called as parasitics. Parasitics can be of two types -resistance and capacitance.

Origin Of Parasitic Resistance

1.Arguably the most challenging aspect of Analog and Mixed Signal design with finFETs is coping with parasitic device, MEOL (middle end of line) and BEOL(back end of line) resistance which is getting worse with each lower technology node.

2.Parasitic device resistance originates from the source/drain, gate, and as well. FinFET source/drain resistance is very high as currents funnel from trench contacts into the narrow fins through a diffusion with limited silicide. Short-channel gate resistance is also high, even with metal gates.

3. The resistance is highest on top of the fin where the gate is already thin and made even thinner after being recessed for SAC formation.

4.Contacting the gate on both sides of an active area and using groups of fewer fins are common area saving techiques to mitigate growing parasitic effects. The use of higher diode current ratios is possible in thermal sensors but requires RD cancellation techniques.

5.Higher well resistance is also responsible for some layout growth due to the higher density of well taps required to prevent latch-up.

6.Finer geometries and adding via tends to add substantially more resistance in the MEOL. Techniques to reduce contact and via resistance are becoming vitally important, even at the expense of increased capacitance. For example, the double-source layout for multi-fingered devices and SAC extension for more diffusion vias are increasingly used to mitigate droop in high-current circuits such as I/O transmitters and clock buffers.

7.The resistance concern extends into the BEOL, especially at the lowest levels with tightest pitch for logic routability. Metal pitch scaling increases resistance at an exponential rate. For example, reducing the metal pitch from 80 to 48 nm results in a 6× increase in line resistance .

Origin Of Parasitic Capacitance

1.The compact 3-D finFET geometry and denser interconnects in the finFETs have increased parasitic capacitance by large.

2. In migrating from planar to finFET CMOS, dynamic power reduction required aggressive VDD scaling to offset the higher capacitance . CGS and CGD are particularly high due to the gate sidewall coupling to the trench SACs and epitaxial source/drain fill between fins, impacting analog design in a variety of ways.

Parasitic Extraction:The process of extracting out interconnect parasitcs from layout using extraction tools is basically parasitic extraction.Interconnect parasitics are stored in file called as SPEF (Standard Parasitic Exchange Format)

StarRC (Synopsys)and Calibre-RC (Mentor Graphics) are common extraction tools used in ASIC flow.

Net Delay Representation In SPEF

Factors Affecting Resistance Of Net

1.Resistance Of Net which depends on sheet resistance,length and width. R=Rs*(L/W) where L= Length of wire; W=Width of wire;Rs=Sheet Resistance 2.Resistance Of Via i.e Number of vias in the net.

FactorsWire Resistance
Layout FactorsRoute Length Increases
Route Width Increases
Process Factors Metal sheet resistance IncreasesIncreases
Factors Wire Capacitance
Layout Factors Route Length Increases
Route Width Increases
Process Factors Oxide Thickness Increases Decreases
Dielectric Constant Increases Increases

Let’s summarize some important points to control parasitics during routing critical nets:

1. Use higher metals for the net for which parasitic capacitance is important.
2. Increase the spacing between the nets in which parasitic capacitance required is less.

3. Put some other reference signal (with which parasitic capacitance is not so important) in between the nets for which the parasitic capacitance required is less.

4.Avoid too much parallel routing of metals.

Here parallel routing means one metal on another metal completely as shown

Signal A (Metal 2) is routed over signal B (Metal 1) in parallel, and causes a large area between the plates A and B, which in turn causes higher parasitic capacitance between the plates

Vacuous success for unbounded window in SystemVerilog Assertions

Today I’d like to unleash few of the unsung features SystemVerilog assertions. As we all know the power of assertions for quickly targeting using vivid types of properties and sequences. Apart from formal verification, even in a SV/UVM based randomized verification, it is always preferable to guard all the generic blocks like arbiters, FIFOs and other custom logic by assertions. This helps in safe guarding design for any corner cases which may involve significant debug cycle.

But one feature of assertions that all of us stumble upon is vacuous passing feature. The implication (|-> or |=>) provides a capability of vacuous passing of assertions. The left hand side of the implication is called the “antecedent” and the right hand side is called the “consequent.” The antecedent is the gating condition. If the antecedent succeeds, then the consequent is evaluated. If the antecedent does not succeed, then the property is assumed to succeed by default. This is called a “vacuous success.” While implication avoids unnecessary error messages, it can produce vacuous successes.

This implies that is an assertion is triggered by satisfying antecedent condition and if the consequent condition never gets satisfied (probably due to use of ‘eventuality’ operator), then the assertion never fails. Consider the following scenario:

We have an arbiter where grant can be asserted after N number of cycles of assertion of request. To verify that we get a grant for each of request, we would have something like following property:

property check();

    @(posedge clk)

    req |-> ##[0:$] gnt;


But here, if the request is asserted and we never get a grant from our arbiter, then this assertion will pass vacuously at the end of sim. Even there could be a testbench timeout which can tell us that something went wrong. Debugging a reason of testbench timeout can be tedious and counter intuitive many times. But if we somehow make this assertion fail during vacuous pass, then it would help greatly in saving debug cycle.

SystemVerilog LRM provides a “strong” operator to notify the assertion failure. As per IEEE 1800-2017, Section 16.12.1:

strong(sequence_expr) evaluates to true if, and only if, there is a nonempty match of the sequence_expr.

It implies that we could exploit the following assertion to match it exactly and eliminate vacuous passes at the end of test. Here, if request is asserted, then we are waiting for at least one nonempty match for grant. The assertion will fail if we see a request and never see a grant.

property check();

    @(posedge clk)

    req |-> strong(##[0:$] gnt);


Since only one match of a sequence_expr is needed for strong(sequence_expr) to hold, a property of the form strong(sequence_expr) evaluates to true if, and only if, the property strong(first_match(sequence_expr)) evaluates to true.

Another way to disable vacuous pass is using system command $assertvacuousoff as described in “Assertion control system tasks” in LRM section 20.12. This works similar to $assertcontrol but at a specifically to disable the vacuous passing.

Note that by default Synopsys VCS does not enable liveliness operators for compilation. We need to add “-assert svaext” to enable these operators.

There exists other operators like s_eventually, eventually etc, which can also be good to use. Refer to the below pages for more information on liveliness checking using assertions.

  1. The power of SVA in SystemVerilog.
  2. Doulos liveliness check properties.
  3. SVA FV tutorial.

Hope that this post helps you in easing out the debug cycles… Happy Diwali..!!

Multi-Patterning Issues At 5nm,7nm.

Optical microlithography is a process very similar to photographic printing. It is used for  transferring circuit patterns into the silicon wafer.The pattern to be replicated on the wafer is  first carved on a mask composed of quartz and chrome features.Light passes through the clear quartz areas and is blocked by the  chrome areas.We use an illuminator (UV light) to shine  light through this mask producing an image of the pattern through the lens  system, which is eventually projected down  into a photo resist coated silicon wafer using a projection system.

Fig. Reference :Lithography Options for the 32 nm Half Pitch Node and Beyond, IEEE spectrum

Now we will discuss about Rayleigh’s Criterion. The Rayleigh criterion specifies the minimum separation between two light sources that may be resolved into distinct objects.According to Rayleigh,critical dimension or resolution is defined in following way:

We can see from the table that the critical  dimension is constantly dropping to a lower and  lower value.The 3 main factors that can reduce the  CD are : 1)Increasing NA 2)Decreasing k1 3)Decreasing λ

Can we really increase NA? Nooo!!!

Reason is when the NA is increased beyond a value (0.93) , it has adverse effects on the depth of focus .NA cannot be increased at the cost of reducing the depth of focus,which will reduce the  sharpness of the image printed .

Second choice is Decreasing λ?

When λis reduced below 193nm it faces a lot of technical issues cost, risk, and most  importantly throughput .

And last is Reducing k1 ? Yess….Reducing k1 is the best option available to reduce the resolution size without affecting  the depth of focus .However in a single patterning the the value of k1 is restricted to a  minimum of 0.25 and cannot go beyond that .So this is achieved using multiple patterning which decreases k1 from 0.25.

The basic idea is that if a pitch of interest is not achievable in a single lithography  step, the design is split over two lithography layers in a way that the minimum pitch  is relaxed with respect to the target pitch. In this way the effective k1 of the total  process (i.e., the combination of the two lithography steps) can drop below the theoretical limit of 0.25 for a single patterning process. The increased pitch size enables higher resolution and better printability.

So how does this process work simply?

The easiest way to implement this is by transferring the first litho step into a hard mask  layer by etch and subsequent imaging and etching of a second photoresist layer. This  litho-etch-litho-etch approach can for instance be achieved either by double trench or  double line patterning.

Double Patterning Scheme:Source : Mentor Graphics


Process variation has become very troublesome at each new lower process node.In the era of multi-patterning, misalignment issues are very common.Three to four misalignment in the pattern can affect capacitance and yield very drastically.

While existing design for manufacturing (DFM) tools takes in to account the kind of variability with reasonable amount of accuracy,but the number of corner cases are increasing at each lower node which are typically addressed by adding extra circuit or margin in the circuit.It also changes the thermal characteristics of design which is particularly troublesome in finfet due to higher power density.

With 7nm and 5nm ,fin height is higher so amount of heat getting trapped is also higher and plus more number of wires getting accumulated in small space can lead to thermal migration effect leading to increase in local temperature .

Hence,double and multi-patterning adds an extra component of variability.At 7nm and 5nm ,back end of line capacitance increases hence RC delay increases which is also performance limiter.

Finfet Basics


A much more efficient device configuration was achieved by using Double gate structure and this was proposed by Sekigawa and Hayashi in 1984.This structure had reduced threshold voltage (Vt) roll-off.This encroachment can be reduced by reducing the silicon film thickness.

Second Order Effects are mostly reduced and also there are other advantages of Finfet.

Advantages Of Finfet

Using High K dielectric materials like HFO,we can reduce channel leakage current.

Shallow Trench Isolation prevents leakage current from source and drain and does not affect the same device as well as adjacent device.

Threshold voltage is less than multi gate devices.

30 % of area is reduced and performance is increased compared to MOSFET.

Feature sizesPossible to pass through the 20nm barrier previously thought as an end point.
PowerMuch lower power consumption allows high integration levels. Early adopters reported 150% improvements.
Operating voltageFinFETs operate at a lower voltage as a result of their lower threshold voltage.
Operating speedOften in excess of 30% faster than the non-FinFET versions.
Static leakage currentTypically reduced by up to 90%
Finfet Design

Source and drain are doped with Boron atom with 1e+20 concentration and fin is doped with phosphorous atom with concentration of 1e+17.Fin length is called as Technology and not the channel length which is calculated using Poisson equation.

Layout Model For Finfet Transistor

Layout is similar to that of conventional MOSFET except that channel width is quantized.

Fin Design Considerations

Fin Width-Determines DIBL(Drain Induced Barrier Lowering).

Fin Height- Limited by etch technology.There is a tradeoff between layout efficiency vs design flexibility.

Fin Pitch-Determines layout area.There is tradeoff between performance vs layout efficiency.

In the next post,I will cover second order effects in detail and how these are reduced in Finfet.

SystemVerilog: Rules for Width Casting and Padding Type

Many a times while making some code in RTL design and testbenches, there arises a need to width-cast a variable/signal into some other type. In SystemVerilog, the width-casting is done by a tick () operator. No, I am not going to explain different types of casting in this post but this write-up is dedicated to some trivial errors that can arise while using width-cast that can result in long hours of debugging…

The SystemVerilog 1800-2012 LRM, Section 6.24.1 describes cast operator as follows:

“If the casting type is a constant expression with a positive integral value, the expression in parentheses shall be padded or truncated to the size specified…

The signedness shall pass through unchanged, i.e., the signedness of the result shall be the self-determined signedness of the expression inside the cast”.

The simple looking statement has a deep meaning. The above snippet makes a good point about the signedness of the result. Let’s take a couple of examples:

Example #1, using “int” type

As “int” type is signed by LRM definition at section 6.11, the MSB of the expression in parentheses dictates the padding. If MSB is zero, there will be zero  padding, and if MSB is one, there will padding with ones.

module top ();

bit clk;

initial begin #15 clk =1 ; #15 $display ("vl_q1 = %h, vl_q2 = %h", u_test.vl_q1, u_test.vl_q2);

$finish; end

test u_test (.clk (clk));


module test (input clk);
int  vl_d = 7;
int vl_q1, vl_q2;

always @ (posedge clk) begin
vl_q1 <= 3'(vl_d) ; //MSB is 3rd bit and is 1 - padding with ones

always @ (posedge clk) begin
vl_q2 <= 4'(vl_d);  // MSB is 4th bit and is 0 - padding with zeroes

%vcs -sverilog t.v -R

Output: Compiler version N-2017.12-SP2-8; Runtime version N-2017.12-SP2-8;  Mar 27 05:00 2019

vl_q1 = ffffffff, vl_q2 = 00000007

As we can see in the above output,

  1. The signal v1_q1 is signed-extended with all 1’s since the MSB (3rd bit) of v1_d was 1’b1.
  2. The signal v1_q2 is signed-extended with all 1’s since the MSB (4th bit) of v1_d was 1’b0.

The result entirely depends on which bit of RHS is used in cast. Let’s see a couple of more instances.

Example #2, using “logic” type

If you use “logic” type which is not signed, there will be zero padding, regardless of MSB.

module top ();
bit clk;
initial begin #15 clk =1 ; #15 $display ("vl_q1 = %h, vl_q2 = %h", u_test.vl_q1, u_test.vl_q2);
$finish; end
test u_test (.clk (clk));

module test (input clk);
logic  [1:0]  vl_d = 3;
logic  [31:0] vl_q1, vl_q2;

always @ (posedge clk) begin
vl_q1 <= 2'(vl_d) ;

always @ (posedge clk) begin
vl_q2 <= 3'(vl_d);

%vcs -sverilog t.v -R
Compiler version N-2017.12-SP2-8; Runtime version N-2017.12-SP2-8;  Mar 27 05:07 2019
vl_q1 = 00000003, vl_q2 = 00000003

Example #3, using “logic signed” type

If you use “logic signed “ type, the MSB /sign bit dictates the padding, similar to type “int.

module top ();
bit clk;
initial begin #15 clk =1 ; #15 $display ("vl_q1 = %h, vl_q2 = %h", u_test.vl_q1, u_test.vl_q2);
$finish; end
test u_test (.clk (clk));

module test (input clk);
logic signed [1:0]  vl_d = 3;
logic  [31:0] vl_q1, vl_q2;

  always @ (posedge clk) begin
vl_q1 <= 2'(vl_d) ;

  always @ (posedge clk) begin

    vl_q2 <= 3'(vl_d);  



%vcs -sverilog t.v -R

Compiler version N-2017.12-SP2-8; Runtime version N-2017.12-SP2-8;  Mar 27 05:13 2019
vl_q1 = ffffffff, vl_q2 = ffffffff

Hope that you have got an idea about how the width-casting works distinctively with different signedness and different width of signals. Let me know in comments if you have and doubt regarding this…

Article credits goes to Solvnet article.



UVM-OVM: Yet another compare issue…

Hi guys, recently we discovered one more bug in UVM and OVM build in compare methods. Previously, I discussed about UVM-OVM: Compare method bugs which was about associative array, this post is related to different object types.

Recently the committee has reported/resolved one more bug in UVM/OVM built-in compare method. Note that the following applies to all the UVM and OVM based simulations.

Continue reading →

UVM: Forcing signals in UVM style

Apologies for a late post… Today I would like to mention about some of the useful HDL signal manipulation methods in UVM.

Have you ever wondered about how the backdoor accesses work in RAL?  We provide a string context path to our RAL based register class and we call some peek/poke API to hierarchically access the signal/register in DUT.

How can we do it in SystemVerilog? Providing a string based path and depositing/reading value based on hierarchical access. This seems to be very difficult using plain SystemVerilog. But this is a game played by something called as DPI/VPI.

UVM provides the backdoor access sub-routines for force/release or read/deposit some vale on any hierarchical path provided in the argument. These functions acts as an interface between SystemVerilog and C code to perform various operations. These functions can not only be used for backdoor accesses, but also for forcing some value in any RTL modules.

Continue reading →

ASIC design flow: File extensions

I would like to describe some of the known file extensions that we usually come across while during the entire cycle of chip design. Mostly are the file formats used by Synopsis tools.

Here are the extensions, let me know if I missed out something 🙂


An ASCII data format, used to describe a standard cell library. Includes the design rules for routing and the Abstract of the cells, no information about the internal netlist of the cells. A LEF file contains the following sections:

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ASIC Design Flow outline (Part-1)

Today, ASIC design flow is a very sophisticated and developed process. The overall ASIC design flow and the various steps within the ASIC design flow have proven to be both practical and robust in multi-millions ASIC designs until now. Let’s discuss about an overview of these steps in the design flow.


Lot of activity from gathering market requirement to deciding the technical aspect is done first. This is the crucial step as it will affect the future of the product. Here, vendors may want to get feedback from potential customers on what they are looking for. Once this is done  final specification sheet with all possible technical details is made and handed over to the next team.

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ASIC Design Flow outline (Part-2)

Continuing from the previous post about ASIC Design Flow Part-1, here is some detail explanation about backend flows.


Backend flow

Continue reading →

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