Tag Archives: uvm

UVM: Forcing signals in UVM style

Apologies for a late post… Today I would like to mention about some of the useful HDL signal manipulation methods in UVM.

Have you ever wondered about how the backdoor accesses work in RAL?  We provide a string context path to our RAL based register class and we call some peek/poke API to hierarchically access the signal/register in DUT.

How can we do it in SystemVerilog? Providing a string based path and depositing/reading value based on hierarchical access. This seems to be very difficult using plain SystemVerilog. But this is a game played by something called as DPI/VPI.

UVM provides the backdoor access sub-routines for force/release or read/deposit some vale on any hierarchical path provided in the argument. These functions acts as an interface between SystemVerilog and C code to perform various operations. These functions can not only be used for backdoor accesses, but also for forcing some value in any RTL modules.

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UVM: How TLM ports work? (The straightforward way)

Continuing from my previous post about “UVM: How the TLM ports work?“, here I am presenting an easy way to understand the mystery. Today we will develop a simple infrastructure in SystemVerilog for the same put port. One can implement a get port in a similar fashion just by changing the direction of argument to the tasks.

Ports are nothing but the lightweight intermediate classes that calls specific tasks from one class to another. We will implement following infrastructure in this example:

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UVM: How TLM ports work? (The arduous way)

Wondering how uvm_ports work? One calls an API (let’s say put task) in some class and it can invoke the API in some other class and that too without creating object of other component! Recently I was studying UVM source code for the same and created a uvm_port type infrastructure in pure SV. Basically it is just a matter of passing handles through associative array. Thought of sharing this to make the understanding simple.

We will develop a put port in SV and believe me the other ports are just different flavors of this port. Here is the infrastructure that we are going to develop:

Blocking put port to implementation port connection

uvm_tlm_if_base // –> abstract class
uvm_port base extends uvm_tlm_if_base //–> Main connection takes place here
uvm_blocking_put_port extends uvm_port_base

object extends void
producer extends object
consumer extends object

env has producer and consumer
ENV: producer.port.connect(consumer.imp_port)

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