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We are a bunch of technical people who loves and share one common passion, “ASIC verification”.

The main purpose of this blog is to provide lots of useful information on ASIC (verification, physical design ,design) and solution of the problems which we are facing day-to-day life.

We will assure you that this BLOG will become the place, where you can visit and  find answers related to ASIC developments, new techniques to solve problems, find something exciting and useful every time.

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9 responses

  1. Good work guys…
    Keep it up..!!
    ☺☻☺☻

    Like

    1. Thanks Hardik. 🙂

      Liked by 1 person

  2. Good Initiative

    If i have any quarries regarding SV and UVM where can i post it.

    Nayan

    Like

    1. Sure. Queries/Discussions are always welcomed. You can post it on any of the blog post. 🙂

      Like

  3. need how memory allocated for struct and union

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    1. The memory allocation in structure and union is similar that to C++. Refer to this post: Structure and union and this discussion: Structure and union for different details.

      Like

  4. // inheritance
    // if i comment int a=5 in class child2 i got output as 3 3 3. if not commented it gives 1 3 3 //as output . is there any memory like diagram to understand this

    class parent;
    int a;
    task disp();
    $display(“Transaction “);
    endtask
    endclass

    class child1 extends parent;
    int a=1;
    task disp();
    $display(” %d”,a);
    endtask
    endclass

    class child2 extends child1;
    int a=5;//comment this and check
    task disp();
    $display(“%d”,a);//why this is not printing 5
    endtask
    endclass

    class child3 extends child2;
    function new(int d);
    a=d;
    endfunction
    task disp();
    $display(“%d”,a);
    endtask
    endclass

    module disp;
    parent p;
    child1 c1;
    child2 c2;
    child3 c3;
    initial begin

    c3=new(3);
     c2=c3;
     c1=c2;
    

    c1.disp();
    c2.disp();
    c3.disp();
    end

    endmodule

    Like

  5. what happen if not declared a class as virtual?i think adding virtual keyword to the methods is enough.but why we are adding virtual to class

    Like

    1. Hi.. Sorry for late response…

      Here when we create object of “child3”, the variable of “child2::a” is getting set to 3. The default value is overridden. So we get the following result:
      c1.disp() -> displays variable a from child1 class = 1
      c2.disp() -> displays variable a from child2 class = 3
      c3.disp() -> displays variable a from child2 class = 3

      Comment out entire line: from child2:
      // int a=5;
      Now then there is only single copy of “a”, that is “child1::a”. So when we set the variable from constructor of child3, then child1::a is getting set and the same variable is displayed three times. So the output comes as follows:
      c1.disp() -> displays variable a from child1 class = 3
      c2.disp() -> displays variable a from child1 class = 3
      c3.disp() -> displays variable a from child1 class = 3

      Comment out the assignment only: from child2:
      int a; // =5;
      Now when we comment out the default assignment in child2 class, then there is still a variable in child2. So when we set the variable from child3, the variable in child2 (child2::a) gets set to 3. So we get the same output:
      c1.disp() -> displays variable a from child1 class = 1
      c2.disp() -> displays variable a from child2 class = 3
      c3.disp() -> displays variable a from child2 class = 3

      Note that the task is not “virtual” so the tasks from individual classes are being called. Now, if the task is virtual then SV checks for the type of object and not the handle. So child3::disp will get called and it will display child2::a variable each time.
      c1.disp() -> disp from child3 displays variable a from child2 class = 3
      c2.disp() -> disp from child3 displays variable a from child2 class = 3
      c3.disp() -> disp from child3 displays variable a from child2 class = 3

      Hope this clears the doubt. 🙂

      Like

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