Reducing Parasitics In Finfet Layouts.

With VLSI industry following Moore’s law for many decades, which says, “the number of transistors on a chip becomes double approximately every two years”,the density of devices on chip has gone high and as all layouts are made by following minimum DRC rules,it gives birth to a new significant effect called as parasitics. Parasitics can be of two types -resistance and capacitance.

Origin Of Parasitic Resistance

1.Arguably the most challenging aspect of Analog and Mixed Signal design with finFETs is coping with parasitic device, MEOL (middle end of line) and BEOL(back end of line) resistance which is getting worse with each lower technology node.

2.Parasitic device resistance originates from the source/drain, gate, and as well. FinFET source/drain resistance is very high as currents funnel from trench contacts into the narrow fins through a diffusion with limited silicide. Short-channel gate resistance is also high, even with metal gates.

3. The resistance is highest on top of the fin where the gate is already thin and made even thinner after being recessed for SAC formation.

4.Contacting the gate on both sides of an active area and using groups of fewer fins are common area saving techiques to mitigate growing parasitic effects. The use of higher diode current ratios is possible in thermal sensors but requires RD cancellation techniques.

5.Higher well resistance is also responsible for some layout growth due to the higher density of well taps required to prevent latch-up.

6.Finer geometries and adding via tends to add substantially more resistance in the MEOL. Techniques to reduce contact and via resistance are becoming vitally important, even at the expense of increased capacitance. For example, the double-source layout for multi-fingered devices and SAC extension for more diffusion vias are increasingly used to mitigate droop in high-current circuits such as I/O transmitters and clock buffers.

7.The resistance concern extends into the BEOL, especially at the lowest levels with tightest pitch for logic routability. Metal pitch scaling increases resistance at an exponential rate. For example, reducing the metal pitch from 80 to 48 nm results in a 6× increase in line resistance .

Origin Of Parasitic Capacitance

1.The compact 3-D finFET geometry and denser interconnects in the finFETs have increased parasitic capacitance by large.

2. In migrating from planar to finFET CMOS, dynamic power reduction required aggressive VDD scaling to offset the higher capacitance . CGS and CGD are particularly high due to the gate sidewall coupling to the trench SACs and epitaxial source/drain fill between fins, impacting analog design in a variety of ways.

Parasitic Extraction:The process of extracting out interconnect parasitcs from layout using extraction tools is basically parasitic extraction.Interconnect parasitics are stored in file called as SPEF (Standard Parasitic Exchange Format)

StarRC (Synopsys)and Calibre-RC (Mentor Graphics) are common extraction tools used in ASIC flow.

Net Delay Representation In SPEF

Factors Affecting Resistance Of Net

1.Resistance Of Net which depends on sheet resistance,length and width. R=Rs*(L/W) where L= Length of wire; W=Width of wire;Rs=Sheet Resistance 2.Resistance Of Via i.e Number of vias in the net.

FactorsWire Resistance
Layout FactorsRoute Length Increases
Route Width Increases
Increases
Decreases
Process Factors Metal sheet resistance IncreasesIncreases
Factors Wire Capacitance
Layout Factors Route Length Increases
Route Width Increases
Increases
Increases
Process Factors Oxide Thickness Increases Decreases
Dielectric Constant Increases Increases

Let’s summarize some important points to control parasitics during routing critical nets:

1. Use higher metals for the net for which parasitic capacitance is important.
2. Increase the spacing between the nets in which parasitic capacitance required is less.

3. Put some other reference signal (with which parasitic capacitance is not so important) in between the nets for which the parasitic capacitance required is less.

4.Avoid too much parallel routing of metals.

Here parallel routing means one metal on another metal completely as shown

Signal A (Metal 2) is routed over signal B (Metal 1) in parallel, and causes a large area between the plates A and B, which in turn causes higher parasitic capacitance between the plates

One response

  1. Hey ,
    It is very good blog on parasitic , by reducing these parasitic we can save a lot of power . As a circuit designer you should always know how you can reduce power layout wise as well. I do layout and ckt both . I know the importance of parasitic

    Liked by 1 person

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