SystemVerilog: Rules for Width Casting and Padding Type

Many a times while making some code in RTL design and testbenches, there arises a need to width-cast a variable/signal into some other type. In SystemVerilog, the width-casting is done by a tick () operator. No, I am not going to explain different types of casting in this post but this write-up is dedicated to some trivial errors that can arise while using width-cast that can result in long hours of debugging…

The SystemVerilog 1800-2012 LRM, Section 6.24.1 describes cast operator as follows:

“If the casting type is a constant expression with a positive integral value, the expression in parentheses shall be padded or truncated to the size specified…

The signedness shall pass through unchanged, i.e., the signedness of the result shall be the self-determined signedness of the expression inside the cast”.

The simple looking statement has a deep meaning. The above snippet makes a good point about the signedness of the result. Let’s take a couple of examples:

Example #1, using “int” type

As “int” type is signed by LRM definition at section 6.11, the MSB of the expression in parentheses dictates the padding. If MSB is zero, there will be zero  padding, and if MSB is one, there will padding with ones.

module top ();

bit clk;


initial begin #15 clk =1 ; #15 $display ("vl_q1 = %h, vl_q2 = %h", u_test.vl_q1, u_test.vl_q2);


$finish; end


test u_test (.clk (clk));


endmodule

module test (input clk);
int  vl_d = 7;
int vl_q1, vl_q2;

always @ (posedge clk) begin
vl_q1 <= 3'(vl_d) ; //MSB is 3rd bit and is 1 - padding with ones
end

always @ (posedge clk) begin
vl_q2 <= 4'(vl_d);  // MSB is 4th bit and is 0 - padding with zeroes
end
endmodule

%vcs -sverilog t.v -R

Output: Compiler version N-2017.12-SP2-8; Runtime version N-2017.12-SP2-8;  Mar 27 05:00 2019

vl_q1 = ffffffff, vl_q2 = 00000007

As we can see in the above output,

  1. The signal v1_q1 is signed-extended with all 1’s since the MSB (3rd bit) of v1_d was 1’b1.
  2. The signal v1_q2 is signed-extended with all 1’s since the MSB (4th bit) of v1_d was 1’b0.

The result entirely depends on which bit of RHS is used in cast. Let’s see a couple of more instances.

Example #2, using “logic” type

If you use “logic” type which is not signed, there will be zero padding, regardless of MSB.

module top ();
bit clk;
initial begin #15 clk =1 ; #15 $display ("vl_q1 = %h, vl_q2 = %h", u_test.vl_q1, u_test.vl_q2);
$finish; end
test u_test (.clk (clk));
endmodule

module test (input clk);
logic  [1:0]  vl_d = 3;
logic  [31:0] vl_q1, vl_q2;

always @ (posedge clk) begin
vl_q1 <= 2'(vl_d) ;
end

always @ (posedge clk) begin
vl_q2 <= 3'(vl_d);
end

endmodule
%vcs -sverilog t.v -R
Compiler version N-2017.12-SP2-8; Runtime version N-2017.12-SP2-8;  Mar 27 05:07 2019
vl_q1 = 00000003, vl_q2 = 00000003

Example #3, using “logic signed” type

If you use “logic signed “ type, the MSB /sign bit dictates the padding, similar to type “int.

module top ();
bit clk;
initial begin #15 clk =1 ; #15 $display ("vl_q1 = %h, vl_q2 = %h", u_test.vl_q1, u_test.vl_q2);
$finish; end
test u_test (.clk (clk));
endmodule

module test (input clk);
logic signed [1:0]  vl_d = 3;
logic  [31:0] vl_q1, vl_q2;

  always @ (posedge clk) begin
vl_q1 <= 2'(vl_d) ;
end

  always @ (posedge clk) begin

    vl_q2 <= 3'(vl_d);  

  end

endmodule

%vcs -sverilog t.v -R

Compiler version N-2017.12-SP2-8; Runtime version N-2017.12-SP2-8;  Mar 27 05:13 2019
vl_q1 = ffffffff, vl_q2 = ffffffff

Hope that you have got an idea about how the width-casting works distinctively with different signedness and different width of signals. Let me know in comments if you have and doubt regarding this…

Article credits goes to Solvnet article.

 

 

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Google photo

You are commenting using your Google account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s

%d bloggers like this: