Multi-Patterning Issues At 5nm,7nm.

Optical microlithography is a process very similar to photographic printing. It is used for  transferring circuit patterns into the silicon wafer.The pattern to be replicated on the wafer is  first carved on a mask composed of quartz and chrome features.Light passes through the clear quartz areas and is blocked by the  chrome areas.We use an illuminator (UV light) to shine  light through this mask producing an image of the pattern through the lens  system, which is eventually projected down  into a photo resist coated silicon wafer using a projection system.

Fig. Reference :Lithography Options for the 32 nm Half Pitch Node and Beyond, IEEE spectrum

Now we will discuss about Rayleigh’s Criterion. The Rayleigh criterion specifies the minimum separation between two light sources that may be resolved into distinct objects.According to Rayleigh,critical dimension or resolution is defined in following way:

We can see from the table that the critical  dimension is constantly dropping to a lower and  lower value.The 3 main factors that can reduce the  CD are : 1)Increasing NA 2)Decreasing k1 3)Decreasing λ

Can we really increase NA? Nooo!!!

Reason is when the NA is increased beyond a value (0.93) , it has adverse effects on the depth of focus .NA cannot be increased at the cost of reducing the depth of focus,which will reduce the  sharpness of the image printed .

Second choice is Decreasing λ?

When λis reduced below 193nm it faces a lot of technical issues cost, risk, and most  importantly throughput .

And last is Reducing k1 ? Yess….Reducing k1 is the best option available to reduce the resolution size without affecting  the depth of focus .However in a single patterning the the value of k1 is restricted to a  minimum of 0.25 and cannot go beyond that .So this is achieved using multiple patterning which decreases k1 from 0.25.

The basic idea is that if a pitch of interest is not achievable in a single lithography  step, the design is split over two lithography layers in a way that the minimum pitch  is relaxed with respect to the target pitch. In this way the effective k1 of the total  process (i.e., the combination of the two lithography steps) can drop below the theoretical limit of 0.25 for a single patterning process. The increased pitch size enables higher resolution and better printability.

So how does this process work simply?

The easiest way to implement this is by transferring the first litho step into a hard mask  layer by etch and subsequent imaging and etching of a second photoresist layer. This  litho-etch-litho-etch approach can for instance be achieved either by double trench or  double line patterning.

Double Patterning Scheme:Source : Mentor Graphics


Process variation has become very troublesome at each new lower process node.In the era of multi-patterning, misalignment issues are very common.Three to four misalignment in the pattern can affect capacitance and yield very drastically.

While existing design for manufacturing (DFM) tools takes in to account the kind of variability with reasonable amount of accuracy,but the number of corner cases are increasing at each lower node which are typically addressed by adding extra circuit or margin in the circuit.It also changes the thermal characteristics of design which is particularly troublesome in finfet due to higher power density.

With 7nm and 5nm ,fin height is higher so amount of heat getting trapped is also higher and plus more number of wires getting accumulated in small space can lead to thermal migration effect leading to increase in local temperature .

Hence,double and multi-patterning adds an extra component of variability.At 7nm and 5nm ,back end of line capacitance increases hence RC delay increases which is also performance limiter.

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