Category Archives: Backend

Finfet Basics


A much more efficient device configuration was achieved by using Double gate structure and this was proposed by Sekigawa and Hayashi in 1984.This structure had reduced threshold voltage (Vt) roll-off.This encroachment can be reduced by reducing the silicon film thickness.

Second Order Effects are mostly reduced and also there are other advantages of Finfet.

Advantages Of Finfet

Using High K dielectric materials like HFO,we can reduce channel leakage current.

Shallow Trench Isolation prevents leakage current from source and drain and does not affect the same device as well as adjacent device.

Threshold voltage is less than multi gate devices.

30 % of area is reduced and performance is increased compared to MOSFET.

Feature sizesPossible to pass through the 20nm barrier previously thought as an end point.
PowerMuch lower power consumption allows high integration levels. Early adopters reported 150% improvements.
Operating voltageFinFETs operate at a lower voltage as a result of their lower threshold voltage.
Operating speedOften in excess of 30% faster than the non-FinFET versions.
Static leakage currentTypically reduced by up to 90%
Finfet Design

Source and drain are doped with Boron atom with 1e+20 concentration and fin is doped with phosphorous atom with concentration of 1e+17.Fin length is called as Technology and not the channel length which is calculated using Poisson equation.

Layout Model For Finfet Transistor

Layout is similar to that of conventional MOSFET except that channel width is quantized.

Fin Design Considerations

Fin Width-Determines DIBL(Drain Induced Barrier Lowering).

Fin Height- Limited by etch technology.There is a tradeoff between layout efficiency vs design flexibility.

Fin Pitch-Determines layout area.There is tradeoff between performance vs layout efficiency.

In the next post,I will cover second order effects in detail and how these are reduced in Finfet.

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