Category Archives: VHDL

Logic to Invert bits of a Variable

  • This post describes  all about simple logic of Invert bits of a variable and it’s configurable from outside.
  • Many times we came across this situation where we want to invert all bits of an variable and than send it to DUT or use for checking purpose.
  • Here is how you do it..

`define width 4                      //Width whatever u want
…..
…..
bit [width-1:0] var  ;             // Variable that we need to invert
bit Invert;                            // This bit decide if 1’b0 -> keep is as it is , 1’b1 -> invert it
….
var = vlaue ;                        // Assign some value
var = var ^ {width{Invert}} ;     // MAIN LOGIC .. Just XOR our bit with same width as of our vaiable


Example :

Suppose value is 5 -> 0101 , width -> 4

  • If Invert bit is -> 1’b0 than  var = 0101 ^ 0000 = 0101      ( Same as input )
  • If Invert bit is -> 1’b1 than   var = 0101 ^ 1111    = 1010      ( Inverted output )

See It’s that simple..

You can configure Invert bit from outside..

Guidelines for Synthesis using VHDL

Hello,

Here are some of the guidelines/rules which will be helpful while writing synthesizable VHDL code:
  • If a signal or a variable is not assigned a value in all possible branches of an IF statement, a latch is inferred. If the intention is not to infer a latch, then the signal or variable must be assigned a value explicitly in all branches of the statement.
  • If a signal or a variable is not assigned a value in all possible branches of a case statement, a latch is inferred. If the intention is not to infer a latch, then the signal or variable must be assigned a value explicitly in all branches of the statement.
  • The only loop supported for synthesis is the for-loop.
  • There are three forms of the wait statement:
    -> wait for time;
    -> wait until condition;
    -> wait on signal-list;
    The wait-until form is the only one supported for synthesis. It is recommended to avoid the use of wait statements for synthesis.

Continue reading →

Verilog & VHDL comparison

Hi everybody,

  • Today, I would like to share with you, some of the differences between VHDL and Verilog.
  • These would not be the syntactical differences, but the power/capability of both the languages is compared.

>>> Both of them are Hardware Descriptive Languages, used to represent the desired functionality of a hardware model as a software program.


1)    While SystemVerilog represents an enhanced version of Verilog generally used to simulate andconfirm the functionality of design (whether design will work as intended or not). VHDL is a concise and verbose language; its roots are based on Ada. Verilog constructs are based approximately 50%  on C and 50% on Ada. For this reason an existing C programmer may prefer Verilog over VHDL



2)      As we know, any language starts with its data types …

  • VHDL is a rich and strongly typed language  and more verbose than Verilog. Its syntax is non-C like and extra coding is required to convert from one data type to another. Some examples of VHDL data types are: bit,bit_vector,std_logic,std_ulogic etc.
  • On the other hand, Verilog data types are very simple, easy to use and very much geared towards modelling hardware structure as opposed to abstract hardware modelling.
  • Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. Some examples of Verilog data types are: reg,wire, integer etc.

Continue reading →

%d bloggers like this: