Category Archives: Verilog

SystemVerilog: Rules for Width Casting and Padding Type

Many a times while making some code in RTL design and testbenches, there arises a need to width-cast a variable/signal into some other type. In SystemVerilog, the width-casting is done by a tick () operator. No, I am not going to explain different types of casting in this post but this write-up is dedicated to some trivial errors that can arise while using width-cast that can result in long hours of debugging…

The SystemVerilog 1800-2012 LRM, Section 6.24.1 describes cast operator as follows:

“If the casting type is a constant expression with a positive integral value, the expression in parentheses shall be padded or truncated to the size specified…

The signedness shall pass through unchanged, i.e., the signedness of the result shall be the self-determined signedness of the expression inside the cast”.

The simple looking statement has a deep meaning. The above snippet makes a good point about the signedness of the result. Let’s take a couple of examples:

Example #1, using “int” type

As “int” type is signed by LRM definition at section 6.11, the MSB of the expression in parentheses dictates the padding. If MSB is zero, there will be zero  padding, and if MSB is one, there will padding with ones.

module top ();

bit clk;


initial begin #15 clk =1 ; #15 $display ("vl_q1 = %h, vl_q2 = %h", u_test.vl_q1, u_test.vl_q2);


$finish; end


test u_test (.clk (clk));


endmodule

module test (input clk);
int  vl_d = 7;
int vl_q1, vl_q2;

always @ (posedge clk) begin
vl_q1 <= 3'(vl_d) ; //MSB is 3rd bit and is 1 - padding with ones
end

always @ (posedge clk) begin
vl_q2 <= 4'(vl_d);  // MSB is 4th bit and is 0 - padding with zeroes
end
endmodule

%vcs -sverilog t.v -R

Output: Compiler version N-2017.12-SP2-8; Runtime version N-2017.12-SP2-8;  Mar 27 05:00 2019

vl_q1 = ffffffff, vl_q2 = 00000007

As we can see in the above output,

  1. The signal v1_q1 is signed-extended with all 1’s since the MSB (3rd bit) of v1_d was 1’b1.
  2. The signal v1_q2 is signed-extended with all 1’s since the MSB (4th bit) of v1_d was 1’b0.

The result entirely depends on which bit of RHS is used in cast. Let’s see a couple of more instances.

Example #2, using “logic” type

If you use “logic” type which is not signed, there will be zero padding, regardless of MSB.

module top ();
bit clk;
initial begin #15 clk =1 ; #15 $display ("vl_q1 = %h, vl_q2 = %h", u_test.vl_q1, u_test.vl_q2);
$finish; end
test u_test (.clk (clk));
endmodule

module test (input clk);
logic  [1:0]  vl_d = 3;
logic  [31:0] vl_q1, vl_q2;

always @ (posedge clk) begin
vl_q1 <= 2'(vl_d) ;
end

always @ (posedge clk) begin
vl_q2 <= 3'(vl_d);
end

endmodule
%vcs -sverilog t.v -R
Compiler version N-2017.12-SP2-8; Runtime version N-2017.12-SP2-8;  Mar 27 05:07 2019
vl_q1 = 00000003, vl_q2 = 00000003

Example #3, using “logic signed” type

If you use “logic signed “ type, the MSB /sign bit dictates the padding, similar to type “int.

module top ();
bit clk;
initial begin #15 clk =1 ; #15 $display ("vl_q1 = %h, vl_q2 = %h", u_test.vl_q1, u_test.vl_q2);
$finish; end
test u_test (.clk (clk));
endmodule

module test (input clk);
logic signed [1:0]  vl_d = 3;
logic  [31:0] vl_q1, vl_q2;

  always @ (posedge clk) begin
vl_q1 <= 2'(vl_d) ;
end

  always @ (posedge clk) begin

    vl_q2 <= 3'(vl_d);  

  end

endmodule

%vcs -sverilog t.v -R

Compiler version N-2017.12-SP2-8; Runtime version N-2017.12-SP2-8;  Mar 27 05:13 2019
vl_q1 = ffffffff, vl_q2 = ffffffff

Hope that you have got an idea about how the width-casting works distinctively with different signedness and different width of signals. Let me know in comments if you have and doubt regarding this…

Article credits goes to Solvnet article.

 

 

SystemVerilog: Use of non-blocking while driving stimulus

This post is about a generally seen practice in any testbench driver. Ever thought that why it is better to use Non-Blocking Assignments (NBA’s) in driver? Let’s see what difference does it create.

As we know that every simulation in Verilog/SV executes according to a pre-defined set of steps known as stratified event queues. These steps are repeated for each an every entity and every time stamp. Let’s first understand the term known as simulation time and time stamp/time slot.

The term simulation time is used to refer to the time value maintained by the simulator to model the actual time it would take for the system description being simulated. The term time is used interchangeably with simulation time.

A time slot encompasses all simulation activity that is processed in the event regions for each simulation time.

Following are the event regions that are executed in each timestamp:

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Verilog: #1 Delay in RTL Designs

Today I would like to share something about the #1 delays in RTL. Occasionally, we model the design by providing an explicit #1 delay to each non-blocking assignment. There are a couple of reasons for doing so.

Let’s have a look at a simple shift register with transport delay of #1 as follows:

`timescale 1ns/1ns
`ifdef ADD_DLY
`define DLY 1
`else
`define DLY 0
`endif

module shift_reg(input d,clk,reset,output reg q);
reg a,b,c;

always @ (posedge clk or posedge reset) begin
if (reset) begin
q <= `DLY 'h0;
end
else begin
a<= #`DLY d;
b<= #`DLY a;
c<= #`DLY b;
q<= #`DLY c;
end
end

endmodule

This will synthesize to a 4-bit shift register as shown below:
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SystemVerilog: Passing Array as parameters

This is a simple post related to passing an array of parameters to module, class or interface, in SystemVerilog.

A parameter is a constant value declared within the module, class or interface. The value of parameter can be used to define a set of attributes for the entity which can alter its behavior as well as its physical representation.

Parameters contains a default value, which can be overridden at the time of instantiation, to alter the behavior of a particular instance. So, we can say parameters are used for generalization of any entity.
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Basic Difference between Event based simulator and Cycle based simulator

Many Times we get confused to this simple topic “Difference between Event based simulator and Cycle based simulator “.

Here’s the explanation Helps you understand this…..


Event Based Simulator :

  • Event-based simulators operate by taking events, one at a time, and propagating them through a design until a steady state condition is achieved.
  • Any change in input stimulus is identified as an event.
  • The design models include timing and functionality.
  • A design element may be evaluated several times in a single cycle because the different arrival times of the inputs and the feedback of signals from downstream design elements.
  • While this provides a highly accurate simulation  environment, the speed of the execution depends on the size of the design and the level of activity within the simulation. For large designs, this can be slow.
Features:   Provides an accurate simulation environment that is timing-accurate, and it is easy to detect glitches in the design.

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Logic to Invert bits of a Variable

  • This post describes  all about simple logic of Invert bits of a variable and it’s configurable from outside.
  • Many times we came across this situation where we want to invert all bits of an variable and than send it to DUT or use for checking purpose.
  • Here is how you do it..

`define width 4                      //Width whatever u want
…..
…..
bit [width-1:0] var  ;             // Variable that we need to invert
bit Invert;                            // This bit decide if 1’b0 -> keep is as it is , 1’b1 -> invert it
….
var = vlaue ;                        // Assign some value
var = var ^ {width{Invert}} ;     // MAIN LOGIC .. Just XOR our bit with same width as of our vaiable


Example :

Suppose value is 5 -> 0101 , width -> 4

  • If Invert bit is -> 1’b0 than  var = 0101 ^ 0000 = 0101      ( Same as input )
  • If Invert bit is -> 1’b1 than   var = 0101 ^ 1111    = 1010      ( Inverted output )

See It’s that simple..

You can configure Invert bit from outside..

Verilog & VHDL comparison

Hi everybody,

  • Today, I would like to share with you, some of the differences between VHDL and Verilog.
  • These would not be the syntactical differences, but the power/capability of both the languages is compared.

>>> Both of them are Hardware Descriptive Languages, used to represent the desired functionality of a hardware model as a software program.


1)    While SystemVerilog represents an enhanced version of Verilog generally used to simulate andconfirm the functionality of design (whether design will work as intended or not). VHDL is a concise and verbose language; its roots are based on Ada. Verilog constructs are based approximately 50%  on C and 50% on Ada. For this reason an existing C programmer may prefer Verilog over VHDL



2)      As we know, any language starts with its data types …

  • VHDL is a rich and strongly typed language  and more verbose than Verilog. Its syntax is non-C like and extra coding is required to convert from one data type to another. Some examples of VHDL data types are: bit,bit_vector,std_logic,std_ulogic etc.
  • On the other hand, Verilog data types are very simple, easy to use and very much geared towards modelling hardware structure as opposed to abstract hardware modelling.
  • Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. Some examples of Verilog data types are: reg,wire, integer etc.

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Improvements in Task and Functions in System Verilog as Compared to Verilog

  • Verilog testbenches are now extinct due to the powerful features provided by SystemVerilog which avoids many of the race conditions which were there in Verilog.
  •  Besides this, SystemVerilog provides major improvements to the facilities available in Verilog.These improvements makes SystemVerilog looks familiar with C,C++.
  •  Also various Object Oriented Programming (OOPS) concepts are incorporated in SystemVerilog which is very much popular in Software Development which makes SystemVerilog,A Hardware Verification Language as Compared to Verilog which is A Hardware Descriptive Language used in developing RTL Designs.

A Verilog Task & Function Flashback:

A simple differentiation in Task and Function in Verilog is that:

Task :

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