Author Archive: abhay chavda

Demo to check that your analysis imports are connected or not..

  • It is very Time consuming to check all the analysis port connections manually.There is very easy solution to this and it’s shown below.
  • There are two methods called get_connected_to and get_provided_to in uvm_port_base class.

get_connected_to :  For an port or export type, this function fills ~list~ with all of the  ports, exports and implementations that this port is connected to

get_provided_toFor an implementation or export type, this function fills ~list~ with all of the ports, exports and implementations that this port is  provides its implementation to.

  • Below is a link of EDAPlayground , This example has a scoreboard with two analysis ports (good_xp and bad_xp). The good_xp is connected, while the bad_xp fails the connection check.

LINK : EXAMPLE for Analysis port connection check

More to come….

 

 

Basic Difference between Event based simulator and Cycle based simulator

Many Times we get confused to this simple topic “Difference between Event based simulator and Cycle based simulator “.

Here’s the explanation Helps you understand this…..


Event Based Simulator :

  • Event-based simulators operate by taking events, one at a time, and propagating them through a design until a steady state condition is achieved.
  • Any change in input stimulus is identified as an event.
  • The design models include timing and functionality.
  • A design element may be evaluated several times in a single cycle because the different arrival times of the inputs and the feedback of signals from downstream design elements.
  • While this provides a highly accurate simulation  environment, the speed of the execution depends on the size of the design and the level of activity within the simulation. For large designs, this can be slow.
Features:   Provides an accurate simulation environment that is timing-accurate, and it is easy to detect glitches in the design.

Continue reading →

Intelligence of streaming operator with Dynamic Arrays

  • Streaming operator may become useful operator if we know how to use it properly.
  • It can basically transfer your data to one variable from another different sized variable in just one line of code
  • I made a demo code of  streaming operator.You can click on below link and directly reach to EDA
  • Change size of dynamic array and play with it..

 LINK  ->>  Streaming Operator Example

Logic to Invert bits of a Variable

  • This post describes  all about simple logic of Invert bits of a variable and it’s configurable from outside.
  • Many times we came across this situation where we want to invert all bits of an variable and than send it to DUT or use for checking purpose.
  • Here is how you do it..

`define width 4                      //Width whatever u want
…..
…..
bit [width-1:0] var  ;             // Variable that we need to invert
bit Invert;                            // This bit decide if 1’b0 -> keep is as it is , 1’b1 -> invert it
….
var = vlaue ;                        // Assign some value
var = var ^ {width{Invert}} ;     // MAIN LOGIC .. Just XOR our bit with same width as of our vaiable


Example :

Suppose value is 5 -> 0101 , width -> 4

  • If Invert bit is -> 1’b0 than  var = 0101 ^ 0000 = 0101      ( Same as input )
  • If Invert bit is -> 1’b1 than   var = 0101 ^ 1111    = 1010      ( Inverted output )

See It’s that simple..

You can configure Invert bit from outside..

Use fork-join_none method in for loop

  • Using threads in loop may be tricky some times and if it’s nested than no words.
  • But As always SV  has solution as “Automatic” keyword.
  • Supoose I want below algorythm to be implimented with for loop.

Than at first we think of this..


for(int i =0 ; i<10 ; i++)begin
 fork begin 
  $display(“#%0t : i = %0d  random_delay =%0d”,$time,i,random_delay);
#random_delay;
  end
  join_none
end
wait fork;


NOTE :  You should never use fork-join_none directly you should write begin – end in it to avoid conflict.

  • Above code will be compile free but don’t give expected output. Check it !! Problem is it will take last value of i (10) in every iteration.
  • instead you should write this..

Continue reading →

Change severity from UVM_ERROR to UVM_INFO

  • Sometimes in you will face situation where you need some of your components from your environment to don’t show error message. You want to disable error from some component.
  • of course you don’t change every uvm_error message to uvm_info..
  • It will take care by one awesome functionality of uvm_report_catcher class.
UVM_REPORT_CATCHER :
  • The uvm_report_catcher is used to catch messages issued by the uvm report server.
  • It means all four message of `uvm_info , `uvm_error , `uvm_warning , `uvm_fatal can be registered and controlled by this class.
  • It will catch messages using callbacks.
  • The uvm_callbacks#(<uvm_report_object>,uvm_report_catcher) class is aliased to “uvm_report_cb” to make it easier to use.

Here is how it’s done..

EXAMPLE :
Continue reading →

Solution of Assertion with variable ## delay

  •  Assertion is the life savior of verification and design engineers . With the help of assertions we could verify more and precisely in very less time.
  •  There are many tricks for writing property of assertion , this topic of the blog will describe one of the tricks of writing assertion.

EXAMPLE

  • There is one input signal ‘a‘ and one output signal ‘b‘.
  •  whatever the value of a is given to b after 10 clock cycle , we need to write property to check it.

It’s quite easy…


property delay_check();              // take all signals as defined in the code 
@(posedge clk)
   disable iff (! rst)                         //  Disable if reset
    a |-> ##10 b;                            
endproperty

===or====
Continue reading →

Why This blog ??

Hi everyone ,

We are a bunch of technical people who loves and share one common passion , “ASIC verification”.

The main purpose of this blog is to provide lots of useful information on ASIC (verification, physical design ,design ) and solution of the problem which we are facing day-to-day life.

We will assure you that this will become the place where you can visit and  find answers on ASIC , new techniques to solve problem , find something exciting and useful every time.

Keep sharing , Keep Exploring

Thanks.

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