Monthly Archives: February, 2018

ASIC design flow: File extensions

I would like to describe some of the known file extensions that we usually come across while during the entire cycle of chip design. Mostly are the file formats used by Synopsis tools.

Here are the extensions, let me know if I missed out something 🙂


An ASCII data format, used to describe a standard cell library. Includes the design rules for routing and the Abstract of the cells, no information about the internal netlist of the cells. A LEF file contains the following sections:

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