Daily Archives: May 20th, 2016

UVM: Enigmatic gambits

Hello friends,

From now onwards, I shall be sharing some day-to-day tricks about UVM methodology. These tricks maybe as simple as explaining about a UVM function usage or can be somewhat trickier creating user-defined APIs.

Following is a list of tricks unrevealed so far:

  1. Tests without Sequence : Executing simple tests without creating sequence.
  2. Drop All Objections : Dropping ALL the raised objections from all components.

accelera uvm

Hope these might be helpful while actual creation of a UVM based testbench. More things to be posted soon.

UVM: Drop All Objections

In continuation with my previous post about Tests without sequence, today I would like to share another situational post about UVM that I came across recently.

The test requirement is framed like this: Whenever a timer (let’s say interrupt timer) gets expired, move out from run_phase and proceed with remaining phases like extract_phase, report_phase etc. In short, whenever timer expires, the sequence should stop execution and simulation should continue to next phases. Something like follows:

// In test
task run_phase(uvm_phase phase);

// In test extract_phase
function extract_phase(uvm_phase phase);
// Check packets, if timer is not expired.
// Else, check whether expiry of timer was valid or not.

// In some other component
task run_phase(uvm_phase phase);
interrupt_timer(); // interrupt timer based on clock pulse count
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