Daily Archives: May 8th, 2016

UVM: Tests without sequence

This post is regarding an unadorned alternative for some straightforward tests in UVM. Lets begin talking about a recent scenario that I faced in a simple UVM test.

The test basically had multiple scenarios and scenario selection was randomized. Each scenario executes a single data traffic sequence and generates a different pulse on different interfaces.

Traditionally, in UVM, we would start the data traffic sequence and then some testcase specific sequence based on selected scenario. Some engineers would also prefer to add a selection/switching logic (bit or something) to testcase specific sequence itself.

The testcase specific sequence will eventually manipulate some fields in transaction class (in randomize with) and generate the required packet. Commonly, something like the following code would do the job.
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