Today I would like to share something about the
#1 delays in RTL. Occasionally, we model the design by providing an explicit
#1 delay to each non-blocking assignment. There are a couple of reasons for doing so.
Let’s have a look at a simple shift register with transport delay of
#1 as follows:
`define DLY 1
`define DLY 0
module shift_reg(input d,clk,reset,output reg q);
always @ (posedge clk or posedge reset) begin
if (reset) begin
q <= `DLY 'h0;
a<= #`DLY d;
b<= #`DLY a;
c<= #`DLY b;
q<= #`DLY c;
This will synthesize to a 4-bit shift register as shown below:
Today, we are interested in behavior of every flipflop, when synthesized on actual hardware. Every flop shall have many timing constraints and limitations. Some of the delays are listed below:
- The setup time is the interval before the clock where the data must be held stable.
- The hold time is the interval after the clock where the data must be held stable. Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured.
- The clock-to-Q propagation delay specifies the amount of time after the rising edge of the clock that Q outputs the new value. Note that the set up and hold is related to input signal and clock edge, not output. While Clk-to-Q delay is with reference to output.
- Contamination delay is the amount of time the output of the combinational logic will stay constant after it’s inputs are changed. After that delay the outputs are contaminated. Propagation delay is the time that combinational logic outputs take to be valid after the input changes.
- The contamination and propagation delay comes into picture when a flip flop is deiven from some combinational logic.
- For sequential logic, the output begins to change after a clock-to-Q contamination delay (tccq) and completely settles after a clock-to-Q propagation delay (tpcq).
Let’s have a look at these delays in a waveform to get a clear picture:
For an edge triggered flip flop, the clock-to-Q time is the time it takes for the register output to be in a stable state after a clock edge occurs. Most high performance flip flops have hold times between 0ps and 800ps. Adding
#1 to RTL models will fix any problems associated with delays in real synthesized design.
Assume that we have three RTL partitions as shown in figure below. One of which is fully compiled and synthesized design with nonzero setup and hold time requirements. While the other two partitions are still in development phase following 0-delay RTL model.
Whenever a positive edge of clock arrives, the 0-delay RTL changes its outputs instantaneously. These updated outputs are available for full clock cycle as inputs to gate level design. Hence, the gate level design can capture the outputs easily on the next clock edge. So, there are no issues related to setup time.
Now, as soon as there is a rising clock edge, the RTL model immediately changes the outputs that are being driven to the gate level model, but the gate level model expected the old data value to be held to meet the hold time requirements. The RTL model changed the gate level inputs in zero-time, violating the hold time requirement of the gate level model. Hence, there are hold time issues with this model.
Coming to Verilog coding part for this modelling. Following type of delay is useful to model clock-to-q delay behavior of circuit:
The time taken by signal to propagate through a net i.e through wire is known as time of flight or transport delay of a wire.
Transport delay models are simulation delay models that pass all pulses, including pulses that are shorter than the propagation delay of corresponding Verilog procedural assignments. Transport delays pass glitches, delayed in time.
Transport delay is useful when modeling behavioral elements where the delay from input to output is of interest. Whenever input changes, output is immediately evaluated and kept in a event queue and assigned to output after specified delay. These type of delay is used to model the clock-to-q delay in RTL.
a <= `DLY d; // Transport delayed assignment
#1 delays to the outputs of the RTL model, the design will hold output values for 1ns. Thereby correctly satisfying hold time requirements of gate level model.
#1 delay have a disastrous impact on performance of simulator, but it is required for modelling real time scenario. The above shift register example is simulated with and without
+define+ADD_DLY switch and results can be viewed. So, in a nutshell, for every large and precise RTL design, the
#1 delay is inevitably used.