Verilog: #1 Delay in RTL Designs

Today I would like to share something about the #1 delays in RTL. Occasionally, we model the design by providing an explicit #1 delay to each non-blocking assignment. There are a couple of reasons for doing so.

Let’s have a look at a simple shift register with transport delay of #1 as follows:

`timescale 1ns/1ns
`ifdef ADD_DLY
`define DLY 1
`define DLY 0

module shift_reg(input d,clk,reset,output reg q);
reg a,b,c;

always @ (posedge clk or posedge reset) begin
if (reset) begin
q <= `DLY 'h0;
else begin
a<= #`DLY d;
b<= #`DLY a;
c<= #`DLY b;
q<= #`DLY c;


This will synthesize to a 4-bit shift register as shown below:


Shift Register

Today, we are interested in behavior of every flipflop, when synthesized on actual hardware. Every flop shall have many timing constraints and limitations. Some of the delays are listed below:

  • The setup time is the interval before the clock where the data must be held stable.
  • The hold time is the interval after the clock where the data must be held stable. Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured.
  • The clock-to-Q propagation delay specifies the amount of time after the rising edge of the clock that Q outputs the new value. Note that the set up and hold is related to input signal and clock edge, not output. While Clk-to-Q delay is with reference to output.
  • Contamination delay is the amount of time the output of the combinational logic will stay constant after it’s inputs are changed. After that delay the outputs are contaminated. Propagation delay is the time that combinational logic outputs take to be valid after the input changes.
  • The contamination and propagation delay comes into picture when a flip flop is deiven from some combinational logic.
  • For sequential logic, the output begins to change after a clock-to-Q contamination delay (tccq) and completely settles after a clock-to-Q propagation delay (tpcq).

Let’s have a look at these delays in a waveform to get a clear picture:

Clock to Q Propagation Delay

Clk-to-Q Delay

Setup and Hold

Setup and Hold Delay

Contamination and Propagation Delay

Screenshot from 2016-03-28 11:22:47

All Delays

For an edge triggered flip flop, the clock-to-Q time is the time it takes for the register output to be in a stable state after a clock edge occurs. Most high performance flip flops have hold times between 0ps and 800ps. Adding #1 to RTL models will fix any problems associated with delays in real synthesized design.

Assume that we have three RTL partitions as shown in figure below. One of which is fully compiled and synthesized design with nonzero setup and hold time requirements. While the other two partitions are still in development phase following 0-delay RTL model.


Mixed RTL Design

Whenever a positive edge of clock arrives, the 0-delay RTL changes its outputs instantaneously. These updated outputs are available for full clock cycle as inputs to gate level design. Hence, the gate level design can capture the outputs easily on the next clock edge. So, there are no issues related to setup time.

Now, as soon as there is a rising clock edge, the RTL model immediately changes the outputs that are being driven to the gate level model, but the gate level model expected the old data value to be held to meet the hold time requirements. The RTL model changed the gate level inputs in zero-time, violating the hold time requirement of the gate level model. Hence, there are hold time issues with this model.

Coming to Verilog coding part for this modelling. Following type of delay is useful to model clock-to-q delay behavior of circuit:

The time taken by signal to propagate through a net i.e through wire is known as time of flight or transport delay of a wire.

Transport delay models are simulation delay models that pass all pulses, including pulses that are shorter than the propagation delay of corresponding Verilog procedural assignments. Transport delays pass glitches, delayed in time.

Transport delay is useful when modeling behavioral elements where the delay from input to output is of interest. Whenever input changes, output is immediately evaluated and kept in a event queue and assigned to output after specified delay. These type of delay is used to model the clock-to-q delay in RTL.

a <= `DLY d; // Transport delayed assignment

By adding #1 delays to the outputs of the RTL model, the design will hold output values for 1ns. Thereby correctly satisfying hold time requirements of gate level model.

Using #1 delay have a disastrous impact on performance of simulator, but it is required for modelling real time scenario. The above shift register example is simulated with and without +define+ADD_DLY switch and results can be viewed. So, in a nutshell, for every large and precise RTL design, the #1 delay is inevitably used.

I have referred FPGA timing tutorialCummings NBA with Delays paper and Sequential Circuit Design as a reference for this post. Hope this will be helpful for digging further into this topic.


profile for sharvil111 at Stack Overflow, Q&A for professional and enthusiast programmers

7 responses

  1. thanks for sharing. this is helpful


    1. Nice to see that. 🙂


  2. super explanation..,great to see this blog


    1. Thanks Kishore.


  3. how will you Live much better via migraine headaches

    pick up StartedSecatd OpiniprofessionalRead points of views in demand healthcare people like you topicsMessage BoardsCnect with, then enjoy proficient help with paycheck a proper lifeInsurance GuideGet all set at alterations to your heath care treatment coveragePhysician DirectoryFind a health care your own diet areatorture CoachTrack your floors, initiates, together with cures. get purposes and look pointers with these software package. DownloadFind concerning:take instruction then comparisons on drugs, dating filipino women non-prescription medications, vitamins, additionally health. have a look of phone and situation.find or guide a pillnourishment or towards a fundamentals or SupplementCheck swimming pool is important Interactionss SafetyEnter, shade, or perhaps imprint on the doctor’s prescription otc junk. Our aid id application will display illustrations or photos that you just can rival therapySave one’s own, read interaction, enroll in federal drug administration monitoring, attain family members single members and also.medication NewsVitamin B12 usually will not help out a couple SeniorsDo mineral tablets bring sports athletes an advantage?very new Schizophrenia meds ApprovedFDA: newer, far more cautioning for NSAIDsNew illegal drug agreed upon for heart FailureMobile knowledge App, supplements, and / or vitamin and mineral information out and about. DownloadOvercome a new concern with civic SpeakingNew hints reasons why Mosquitos bout Youirs tax. ACHOO,flash wellness and fitness: have a go at the main 7 Minute WorkoutHave useful pearly white’s? experience get the right Do16 guidelines to help you Get sorted.


  4. […] Exemplo de registrador de deslocamento de 4 bits. Fonte: ASIC Design. […]


  5. […] Example of 4-bit shift register. Source: ASIC Design. […]


Leave a Reply

Fill in your details below or click an icon to log in: Logo

You are commenting using your account. Log Out /  Change )

Google photo

You are commenting using your Google account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s

%d bloggers like this: