Many Times we get confused to this simple topic “Difference between Event based simulator and Cycle based simulator “.
Here’s the explanation Helps you understand this…..
Event Based Simulator :
- Event-based simulators operate by taking events, one at a time, and propagating them through a design until a steady state condition is achieved.
- Any change in input stimulus is identified as an event.
- The design models include timing and functionality.
- A design element may be evaluated several times in a single cycle because the different arrival times of the inputs and the feedback of signals from downstream design elements.
- While this provides a highly accurate simulation environment, the speed of the execution depends on the size of the design and the level of activity within the simulation. For large designs, this can be slow.
Features: Provides an accurate simulation environment that is timing-accurate, and it is easy to detect glitches in the design.
Limitations: The speed depends on the size of the design and the level of activity within the simulation. If the designs are large, the simulation speed may be slow. The speed is limited because event-based simulators use complex algorithms to schedule events, and they evaluate the outputs multiple times.
Cycle Based Simulator :
- Cycle-based simulators have no notion of time within a clock cycle.
- They evaluate the logic between state elements and/or ports in the single shot.
- each logic element is evaluated only once per cycle, this can significantly increase the speed
of execution, but this can lead to simulation errors.
- Cycle-based simulators only function on synchronous logic.
Features: Provides speeds of 5x to 100x times that of event-based simulators. The simulation speed can be up to 1000 cycles per second for large designs. Best suited for designs requiring large simulation vectors, such as microprocessors, application- specific integrated chips (ASIC), and SOCs.
Limitations: Cannot detect glitches in the design, since they respond only to the clock signal. Also they do not take the timing of the design into consideration, therefore, timing verification needs to be performed using a static-timing analysis tool.
Reference : Kluwer Academic – System-On-A-Chip Verification – Methodology And Techniques