SystemVerilog Terms: ‘function static’ and ‘static function’

Hi friends,

Today I would like to share something about SystemVerilog functions.
Not about that ‘static‘ and ‘automatic‘ is just some more about ‘function static‘ and ‘static function

By default, when you call a function of any class, that function may have its own temporary variables which are initialized every-time you call the function. But, in some cases, you just want to have a count of “How many times the function is actually called..??” or you may want to preserve the last value of your functions local variable then it goes a bit tricky, or rather some logical cheat may help you out.
static function‘ is a function whose scope is static. I mean, a static function remains same for ALL the objects of a class. In system memory, the function is stored at a single place and all the objects access that function memory.
But this type of function has…what I call as a glitch in it. What if I want to access other automatic variables of the class…?? I just can’t. A static function can only access static variables of a class.

When a simple ‘function‘ is called from different objects then all the internal variables are initialized to their default values for each individual object’s function call.

function static‘ is another type of function that makes the scope of its internal variables as static. This type of function DO NOT initialize its variables during each call..!!
The scope of internal variables of function becomes static. Rest of the class variables scope remains the same (auto).
So, now I can access all the static and automatic variables of class..!!
All the automatic variables of class are initialized for every object, but the function’s internal variables remains static.

This is something you may want for performing recursive calculations in every function call. Remember “POSITION MATTERS” 😉

Here’s a link for sample code I’ve shared…
And ya, edaplayground has got a new VCS-2014 simulator option; awesome!!!!!
Function static & Static function

Thanks for tolerating me.. 🙂
Next post about constraint types coming soon…


profile for sharvil111 at Stack Overflow, Q&A for professional and enthusiast programmers

7 responses

  1. Its like you read my mind! You seem to know a lot
    approximately this, such as you wrote the guide in it or
    something. I believe that you simply can do
    with a few % to power the message home a little bit, however instead of that, this is wonderful blog.
    An excellent read. I’ll certainly be back.


    1. Nice to hear that.
      Thanks Jason. 🙂


  2. Sharvil,

    Very nice explanation with simple example. You are doing great by sharing your knowledge.

    Harshit Patel


    1. Thanks Harshit. 🙂


  3. can u plzz explain this problem

    task t1();

    data = x;


    task t2();

    y = data;


    @(posedge clk)


    @(posedge clk)


    Will above logic work or is there any gotcha in that? Consider that there are other

    logics inside tasks and while calling tasks also.


    1. Assuming that both posedge of clocks are concurrent blocks, the tasks t1 and t2 are invoked concurrently at the same time, so a race condition exists that whether data will be updated first or y will be updated first. Now it depends on the simulator that which thread is to be executed first. A similar question is posted over here.

      To avoid such type of race conditions, a semaphore or event can be used. Refer to this link for basics of events in SystemVerilog.


      1. Thanks for pin me.


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