Here are some of the guidelines/rules which will be helpful while writing synthesizable VHDL code:
- If a signal or a variable is not assigned a value in all possible branches of an IF statement, a latch is inferred. If the intention is not to infer a latch, then the signal or variable must be assigned a value explicitly in all branches of the statement.
- If a signal or a variable is not assigned a value in all possible branches of a case statement, a latch is inferred. If the intention is not to infer a latch, then the signal or variable must be assigned a value explicitly in all branches of the statement.
- The only loop supported for synthesis is the for-loop.
- There are three forms of the wait statement:
-> wait for time;
-> wait until condition;
-> wait on signal-list;
The wait-until form is the only one supported for synthesis. It is recommended to avoid the use of wait statements for synthesis.
- Component instantiation statements are used when a designer is not satisfied with the quality of circuits produced by a synthesis tool.
- Conversion functions do not represent hardware, it is important to find out the built-in conversion functions and use only where necessary.
- It’s very useful in practice to identify common sub-expressions to reuse computed values where possible. Use parenthesis to control the structure of the synthesized logic.
- Check to see if there are any signals that are being assigned a value and then later on read in to the process. To prevent simulation mismatches, it is better to model such temporaries as variables.
- Delays are ignored by synthesis tools. This may cause a mismatch in simulation results. So it is recommended to avoid inserting delays into a model that is to be synthesized.
- A process with an incomplete sensitivity list causes simulation mismatches. Include all signals read in the process in the sensitivity list of the process.
- Synthesis tools ignore initial values specified for a variable or a signal in its declaration. This can cause a mismatch in simulation results, avoid inserting delays into a model that is to be synthesized.
- By limiting module size, a designer gains in both the synthesizer run-time and the quality of the synthesis results.
- The synthesizer does much better on logic that is contained within one entity. If a certain timing path travels through 4 separate modules, the synthesizer will make its best effort within each of the modules, but the overall results won’t be as good as the case where the whole path is in a single module.
- Notice that there is a trade-off between the two rules of partitioning. The synthesizer always does better on smaller sized modules, however it also does better when all of a path’s logic is contained within one module.
Please comment for any query.