- Today, I would like to share with you, some of the differences between VHDL and Verilog.
- These would not be the syntactical differences, but the power/capability of both the languages is compared.
>>> Both of them are Hardware Descriptive Languages, used to represent the desired functionality of a hardware model as a software program.
1) While SystemVerilog represents an enhanced version of Verilog generally used to simulate andconfirm the functionality of design (whether design will work as intended or not). VHDL is a concise and verbose language; its roots are based on Ada. Verilog constructs are based approximately 50% on C and 50% on Ada. For this reason an existing C programmer may prefer Verilog over VHDL
2) As we know, any language starts with its data types …
- VHDL is a rich and strongly typed language and more verbose than Verilog. Its syntax is non-C like and extra coding is required to convert from one data type to another. Some examples of VHDL data types are: bit,bit_vector,std_logic,std_ulogic etc.
- On the other hand, Verilog data types are very simple, easy to use and very much geared towards modelling hardware structure as opposed to abstract hardware modelling.
- Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. Some examples of Verilog data types are: reg,wire, integer etc.
3) After data types, the language requires operators…
- Majority of the operators are same between the two languages.
- Verilog does have very useful unary reduction operators that are not in VHDL. A loop statement can be used in VHDL to perform the same operation as a Verilog unary reduction operator.
- On the contrary, VHDL has the mod operator that is not found in Verilog.
4) Structural modelling is also an important aspect..
- In VHDL, a specific bit width model can be instantiated from a generic n-bit model using the generic statement. The generic model will not synthesize until it is instantiated and the value of the generic given
- A specific width model can be instantiated from a generic n-bit model using overloaded parameter values. The generic model must have a default parameter value defined This means two things. In the absence of an overloaded value being specified, it will still synthesize,but will use the specified default parameter value
- it does not need to be instantiated with an overloaded parameter value specified, before it will synthesize.User defined constructs include the use of user defined truth tables.
- VHDL is generally used for abstract level architecture. Hence User Defined Primitives (UDP’s) are not available.The Verilog language was originally developed with gate level modelling in mind, and so has very good constructs for low level modelling. For example, User Defined Primitives (UDP),truth tables and the specify block for specifying timing delays across a module.
5) In terms of design re-usability, VHDL has an advantage.
- VHDL Procedures and functions may be placed in a package so that they are available to any design-unit that wishes to use them.
- While there is no concept of packages in Verilog (though SystemVerilog supports ackages).Functions and tasks used within a model must be defined in the module.To make functions and tasks accessible from different modules, they must be placed in a separate system file and included using the `include compiler directive.Verilog is easy to grasp as compared to VHDL.
6) Other differences…
- VHDL may seem less intuitive at first, since it is very strongly typed; a feature that makes it robust and powerful for the advanced user after a longer learning phase.
- Verilog is probably the easiest to grasp and understand, except for PLI interface which can be thought of as an entirely different language.Abstract constructs are always beneficial.
- There are more constructs and features for high-level modelling in VHDL than Verilog. For example package statements, configuration statements etc.
- Except for being able to parametrize models by overloading parameter constants, there is no equivalent to the high-level VHDL modelling statements in Verilog.Verboseness of a language is a comfort region for the programmer.
- Because VHDL is a very strongly typed language models must be coded precisely with defined and matching data types.
- bit_vector of width [7:0] cannot be assigned to a bit_vector of width [15:0] in VHDL
- While in Verilog, signals representing objects of different bits widths may be assigned to each other.
- The signal representing the smaller number of bits is automatically padded out to that of the larger number of bits, and is independent of whether it is the assigned signal or not.Unused bits will be automatically optimized away during the synthesis process.
- reg of width [7:0] can be assigned to reg of [15:0] width.
So, the question remains, which language is preferable…??
>>> The answer lies in the individuals comfort with any of those languages.
>>> Again, looking at history of the two languages, we find that VHDL came earlier and got quickly adopted by the industry quite vastly. But Verilog, being a forgiving language makes it easier for the designer to code and found many other advantages in comparison with VHDL. Hence, later designs made use of Verilog.