Improvements in Task and Functions in System Verilog as Compared to Verilog

  • Verilog testbenches are now extinct due to the powerful features provided by SystemVerilog which avoids many of the race conditions which were there in Verilog.
  •  Besides this, SystemVerilog provides major improvements to the facilities available in Verilog.These improvements makes SystemVerilog looks familiar with C,C++.
  •  Also various Object Oriented Programming (OOPS) concepts are incorporated in SystemVerilog which is very much popular in Software Development which makes SystemVerilog,A Hardware Verification Language as Compared to Verilog which is A Hardware Descriptive Language used in developing RTL Designs.

A Verilog Task & Function Flashback:

A simple differentiation in Task and Function in Verilog is that:

Task :

  • A Task Consumes time, it can consume time to process the code in it , can contain delay statements and blocking statements such as @posedge or @negedge.
  • A Task has zero or more inputs and outputs.
  • A Task is synthesizable only if it does not consumes time.

Function :

  • A function does not consumes time , that is it cannot contain delays , blocking statements.
  • A function cannot call a task (As task contains delays).
  • A function must return a value ,value must be used in assignment statement.But it returns only single value (output or inout are not used with functions)A function is synthesizable.

Furthermore,

Task and Function in verilog uses “begin…end” blocks inside them.

In Verilog , Arguments in tasks are handled very simply i.e input and inout are copied to local variable at the start of routine and return values are copied to output or inout at the end of routine.Hence we cannot pass memories(arrays or queues) in verilog task , arguments must be scalars.

Improvements in Systemverilog Task & Function :

Systemverilog has made significant changes in Task and Functions the way they were in Verilog 1995 and Verilog 2001.
Basic difference related to delay between Task and function remains the same here also.

1: It is optional to use “begin…end” block in task and functions in SV.  task…endtask , function…endfunction  blocks are sufficient .

2: If routines does not contain any input or output , it is not necessary to use empty parenthesis () while calling the routine.

3: Void Function : In SystemVerilog task that does not consume time is written as void function , void represents it is function that does not return a value which was not possible in verilog function.
Void function can be called from task as well as function.

4: If you want to ignore the return value of function ,simply cast it to “void” type.

5: We can pass memories in task and functions such as arrays and queues.

6: SystemVerilog introduces “ref” variable to pass arguments by reference.

7: Task has by default argument direction “input logic” and it is sticky.

8: Default values to the arguments.

9: Not only you can pass arrays and queues , you can also use them as return type in functions and output/input in tasks.

  • All these efforts reduces the size and time required to create testbenches with less repetitions of code, by making it familiar with other programming language like C, C++.
  • I will highlight and show all of the above mentioned improvements in the upcoming posts , which will help in writing efficient codes in SV.
  • This will be very helpful for the freshers in the ASIC field who are not familiar with SV and will clear all confusions regarding task and function differences in SV and Verilog.This will also be helpful during interviews because such questions are asked very frequently in most of the interviews.

In case any query regarding Verilog,SystemVerilog and UVM , you can write it in the comment area or mail me at

Email ID : gaurang.pandey@einfochips.com

2 responses

  1. why do we use write function and why not write task in analysis port concept.

    Liked by 1 person

    1. The analysis ports are mainly used as boradcasters. So, generally they transfer data to multiple recipients. uvm_analysis_port class in UVM BCL has a ‘function’ write and not a task. This might be mainly because that if a write task is provided, then multiple recipients can have varying delay in their implementation tasks and hence the producer could get stuck. By using a function, the producer is guaranteed to move forward to capture new data in the next timestamp.
      Refer to uvm_analysis_port for more information about write function.

      Like

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